Design Verification Engineer

Company Overview

Company details are not specified.

Job Summary

The Design Verification Engineer will play a crucial role in ensuring the quality and functionality of design specifications through rigorous verification processes. This position emphasizes individual contribution and collaboration within a dynamic team environment to meet organizational goals.

Responsibilities

• Develop and implement test plans and test benches for design verification using SystemVerilog and UVM.
• Collaborate with design teams to understand specifications and requirements for IOMMU.
• Execute verification tests, analyze results, and provide recommendations for design improvements.
• Document verification processes and results to ensure compliance with industry standards.
• Communicate effectively with team members and stakeholders regarding progress and challenges.

Qualifications

• Minimum of 5+ years of design verification experience.
• Strong hands-on expertise in SystemVerilog and UVM (Universal Verification Methodology).
• At least 2–3 years of experience working on IOMMU (Input-Output Memory Management Unit).
• Excellent communication skills and a positive attitude to work in a collaborative environment.
• Ability to work independently as a strong individual contributor.

Preferred Skills

• Familiarity with other verification methodologies and tools.
• Knowledge of additional programming languages is a plus.
• Experience with functional coverage and assertion-based verification.

Experience

• A minimum of 5 years of relevant experience in design verification.

Environment

• Work location: Bangalore.
• The work setting may include collaboration with cross-functional teams in an office environment.

Salary

Salary details are not specified.

Growth Opportunities

Opportunities for career advancement and professional development are not specified.

Benefits

Benefits offered are not specified.