RTL Design Engineer

Company Overview

Not specified.

Job Summary

We are seeking a skilled RTL Design Engineer specializing in Synthesis, Lint, and Clock Domain Crossing (CDC) to contribute effectively to our design and development team. The successful candidate will work on various digital design projects, ensuring high-quality synthesis and verification processes.

Responsibilities

• Develop and optimize RTL designs for various projects.
• Perform synthesis and ensure compliance with design specifications.
• Conduct Lint checks to identify and resolve potential design issues.
• Analyze and implement solutions for Clock Domain Crossing (CDC) scenarios.
• Collaborate with cross-functional teams to ensure integration and functionality of designs.
• Document design processes and results for future reference and team knowledge sharing.

Qualifications

• Education: Bachelor's degree in Electrical Engineering, Computer Science, or a related field.
• Proficiency in RTL design languages such as Verilog or VHDL.
• Strong understanding of synthesis tools and methodologies.
• Familiarity with Lint tools and practices.
• Knowledge in CDC analysis and strategies.
• Excellent problem-solving skills and attention to detail.
• Ability to work collaboratively in a team-based environment.
• Strong communication skills, both verbal and written.

Preferred Skills

• Experience with simulation tools like ModelSim or Questa.
• Familiarity with FPGA and ASIC design processes.
• Knowledge of low-power design techniques.

Experience

• Minimum of 2.5 years of experience in RTL design, synthesis, and verification.

Environment

The position is based in Hyderabad. Specific details about remote or hybrid work options are not provided.

Salary

Not specified.

Growth Opportunities

Not specified.

Benefits

Not specified.