DFT Engineers

Company Overview

Company Overview details are not provided.

Job Summary

We are seeking experienced DFT Engineers with strong expertise in Scan, ATPG, and MBIST for System on Chip (SoC) and Application-Specific Integrated Circuit (ASIC) designs. The primary focus of this role is on the implementation, pattern generation, and verification of DFT features to ensure high test coverage and silicon readiness.

Responsibilities

• Implement and verify Scan, ATPG, and MBIST for complex SoCs.
• Perform pattern generation, coverage analysis, and debugging activities.
• Integrate and validate MBIST with appropriate memory test algorithms.
• Coordinate with Register Transfer Level (RTL) and Physical Design teams for smooth DFT integration and signoff.
• Develop automation scripts to streamline DFT flows.

Qualifications

• Minimum 4 years of DFT experience in ASIC/SoC environments.
• Hands-on expertise with Electronic Design Automation (EDA) tools such as:
  • Synopsys (DFT Compiler, TestMAX, TetraMAX)
  • Cadence Modus
• Strong understanding of fault models (e.g., stuck-at, transition, path delay).
• Knowledge of MBIST architecture and memory test techniques.
• Scripting proficiency in TCL, Perl, or Python.
• Familiarity with RTL design flows, Static Timing Analysis (STA) constraints, and silicon bring-up.

Preferred Skills

• Experience with Siemens Tessent or FastScan tools would be a plus.

Experience

• Candidates should have a minimum of 4 years of relevant experience.

Environment

• This position is based in Bangalore and requires onsite presence.

Salary

Salary details are not provided.

Growth Opportunities

Growth opportunities within the company are not specified.

Benefits

Benefits information is not provided.