Design Verification Engineer

Company Overview

Company details not specified.

Job Summary

The Design Verification Engineer is responsible for developing and implementing verification environments for System on Chip (SoC) and Intellectual Property (IP) verification. This role plays a critical part in ensuring the functionality and reliability of designs through rigorous testing and validation processes.

Responsibilities

• Develop verification environments for SoC and IP designs.
• Implement test bench components to facilitate comprehensive testing.
• Create and implement test cases to validate design functionality.
• Execute functional coverage to ensure all scenarios are tested.
• Implement assertions to catch design errors early in the verification process.
• Conduct failure analysis and debugging to identify and resolve issues efficiently.

Qualifications

• 4 to 10 years of experience in design verification.
• Strong skills in verification environment development and test bench components.
• Proficient in implementing test cases and functional coverage.
• Experience with assertions and debugging techniques.
• Knowledge of protocols including Gen6 PCIe, CXL, Ethernet, and UCIe.
• Relevant educational background in Electrical Engineering, Computer Engineering, or a related field.

Preferred Skills

• Familiarity with industry-standard verification tools and methodologies.
• Experience with SystemVerilog, UVM, or similar verification languages.

Experience

• 4 to 10 years of experience in design verification, specifically within SoC and IP verification.

Environment

Work setting and location details not specified.

Salary

Salary information not specified.

Growth Opportunities

Career advancement opportunities not specified.

Benefits

Benefits information not specified.