Design for Test (DFT) Engineer

Company Overview

[Company overview not specified.]

Job Summary

The Design for Test (DFT) Engineer will be responsible for developing and implementing DFT architectures that enhance test coverage and fault detection in integrated circuits. This role entails collaborating with various teams to integrate DFT logic within chip designs, ensuring that the designs meet rigorous testability requirements.

Responsibilities

• Develop and implement DFT architectures, including scan insertion, Memory Built-In Self-Test (MBIST), and JTAG/IJTAG.
• Perform Automatic Test Pattern Generation (ATPG) with and without timing to maximize test coverage across designs.
• Run and analyze timing-aware and no-timing ATPG simulations to validate fault models and assess test coverage.
• Own the setup and simulation of Hierarchical Module (HM) level ATPG, ensuring that test structures are scalable and reusable.
• Conduct coverage analysis for stuck-at, transition, and path delay faults, providing feedback for design enhancements.
• Collaborate with Register Transfer Level (RTL), Physical Design (PD), and validation teams to integrate and verify DFT logic within the chip.
• Support silicon bring-up and validate test patterns on Automated Test Equipment (ATE).
• Document DFT implementation flows, methodologies, and best practices to standardize processes.

Qualifications

• Strong experience in ATPG for stuck-at and transition faults, both with and without timing considerations.
• Solid understanding of DFT coverage metrics and analysis techniques.
• Hands-on experience with scan insertion, MBIST architecture, and verification processes.
• Proficiency in setting up and managing HM-level ATPG flows and simulations.
• Experience with JTAG/IJTAG implementation and integration within chip designs.
• Familiarity with industry-standard tools such as Synopsys DFTMAX, TetraMAX, Cadence Modus, or Siemens Tessent.
• Scripting proficiency in TCL, Perl, or Python for automation and flow development.
• A relevant degree in Electrical Engineering, Computer Engineering, or a related field is preferred.

Preferred Skills

• Experience with advanced fault simulation and diagnosis techniques.
• Understanding of the overall semiconductor design and manufacturing process.

Experience

• A minimum of 3-5 years of relevant experience in DFT methodologies and ATPG analysis is preferred.

Environment

• The typical work setting is an office environment, with flexibility for hybrid work arrangements as required.

Salary

[Salary information not specified.]

Growth Opportunities

[Opportunities for career advancement within the company not specified.]

Benefits

[Benefits offered by the company not specified.]