DV Engineer

Job Summary

The Design Verification (DV) Engineer will play a crucial role in ensuring the functionality and quality of digital designs. The individual will work as an individual contributor, focusing on verification processes using strong SystemVerilog (SV) and Universal Verification Methodology (UVM) skills. This position is essential for maintaining the organization's commitment to delivering high-quality digital products.

Responsibilities

• Develop and execute verification plans for digital designs.
• Implement test benches and perform simulations to verify design functionality.
• Collaborate with design engineers to identify and resolve design issues.
• Utilize SV/UVM methodologies to create and enhance verification environments.
• Document verification processes and results for future reference and continuous improvement.
• Stay updated with the latest industry standards and verification techniques.

Qualifications

• Bachelor's or Master's degree in Electronics, Computer Engineering, or a related field.
• 8-12 years of experience in design verification.
• Strong proficiency in SystemVerilog and UVM.
• Excellent coding skills in any programming language.
• Strong fundamental understanding of digital design concepts.

Preferred Skills

• Familiarity with various communication protocols.
• Experience with scripting languages such as Python or Perl.
• Knowledge of digital design tools and simulation software.

Experience

• A minimum of 8-12 years of relevant experience in design verification.
• Experience working as an individual contributor in a similar role.

Environment

• Location: Bangalore, Pune, Hyderabad.
• Work Setting: Hybrid model, 3 days in-office per week.
• Employment Type: Contractual, Full-Time.

Start Date

• This position is available immediately.

Deadline

• Applications accepted until April 14, 2025.