Design Verification

Company Overview

Information regarding the company is not specified.

Job Summary

The Design Verification Engineer will play a crucial role in ensuring the correctness and reliability of complex IP or subsystem designs. The successful candidate will be responsible for executing thorough verification processes, which are vital for maintaining high-quality standards in the organization’s product offerings.

Responsibilities

• Execute IP verification and subsystem verification for complex blocks.
• Develop and implement testbenches, test plans, and coverage models utilizing SystemVerilog (SV) and Universal Verification Methodology (UVM).
• Verify Fabric/NOC/Interconnect blocks to ensure design integrity and performance.
• Understand and apply various protocols such as the AMBA suite (AXI/ACE), PCIe, CXL, interrupt handling, and power management in verification processes.
• Collaborate with cross-functional teams to resolve issues related to design verification.
• Perform coherent traffic verification as needed.

Qualifications

• Experience: 5+ years in design verification.
• Technical Skills:
  • Proficiency in SystemVerilog (SV) and Universal Verification Methodology (UVM).
  • Strong understanding of IP verification processes and methodologies.
  • Familiarity with various communication protocols (AMBA, PCIe, CXL).
• Soft Skills: Strong analytical skills, attention to detail, and effective communication abilities.
• Education: Bachelor’s or Master’s degree in Electrical Engineering or related field.

Preferred Skills

• Knowledge of coherent traffic verification is a plus.

Experience

• Minimum of 5 years in relevant design verification roles.

Environment

• Work location is in Bangalore.

---

DFT Engineer

Company Overview

Information regarding the company is not specified.

Job Summary

The DFT (Design for Test) Engineer will focus on implementing design-for-testability features in various components of digital designs. This includes executing tasks related to scan insertion, ATPG pattern generation, and post-silicon debugging to enhance the test coverage and reliability of integrated circuits.

Responsibilities

• Implement various DFT aspects including scan insertion, memory built-in self-test (MBIST), and JTAG.
• Generate ATPG patterns and validate them at both block level and full chip level.
• Validate DFT concepts including timing analysis and sign-off.
• Work with boundary scan architectures, scan compression techniques, and insertion of test points.
• Generate scan patterns and coverage statistics for various fault models, including stuck-at and transition faults.
• Conduct ATPG coverage analysis and address cross-functional issues related to RTL integration and synthesis.
• Utilize Synopsys tools including DFT MAX and TetraMAX, along with VCS for simulations.
• Debug gate level pattern simulations and be involved in post-silicon debug processes.

Qualifications

• Experience: 5+ years in DFT engineering.
• Technical Skills:
  • Comprehensive knowledge of DFT concepts (scan insertion, ATPG).
  • Familiarity with Verilog and RTL simulation.
  • Experience with Spyglass DFT tool.
• Soft Skills: Analytical thinking and problem-solving capabilities, along with effective team collaboration.
• Education: Bachelor’s or Master’s degree in Electrical Engineering or related field.

Preferred Skills

• Exposure to post-silicon debug is a plus.

Experience

• Minimum of 5 years in relevant DFT roles.

Environment

• Work location is in Bangalore.